Task state segment
The task state segment (TSS) is a special segment which holds information about a task. It is used by the operating system kernel for task management. Specifically, the following information is stored in the TSS:
- Processor register state
- I/O port permissions
- Inner-level stack pointers
- Previous TSS link
Location of the TSS::
The TSS may reside anywhere in memory. A special segment register called the task register (TR) holds a segment selector that points to a valid TSS segment descriptor which resides in the GDT (a TSS descriptor may not reside in the LDT). Therefore, to use a TSS the following must be done by the operating system kernel:
- Create a TSS descriptor entry in the GDT
- Load the TR with a segment selector for that segment
- Add information to the TSS in memory as needed
For security purposes, the TSS should be placed in memory that is accessible only to the kernel.
The TR register is a 16-bit register which holds a segment selector for the TSS. It may be loaded through the LTR instruction. LTR is a privileged instruction and acts in a manner similar to other segment register loads. The task register has two parts: a portion visible and accessible by the programmer and an invisible one that is automatically loaded from the TSS descriptor
The TSS may contain saved values of all the x86 registers. This is used for task switching. The operating system may load the TSS with the values of the registers that the new task needs and after executing a hardware task switch (such as with an IRET instruction) the x86 CPU will load the saved values from the TSS into the appropriate registers. Note that some modern operating systems such as Windows and Linux do not use these fields in the TSS as they implement software task switching.