S-R Flip Flop
It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E= 1 but there is no change in the output if E = 0.
||S = R = 0 : No change
- If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
- Hence R’ and S’ both will be equal to 1. Since S’ and R’ are the input of the basic S-R latch using NAND gates, there will be no change in the state of outputs.
||S = 0, R = 1, E = 1
- Since S = 0, output of NAND-3 i.e. R’ = 1 and E = 1 the output of NAND-4 i.e. S’ = 0.
- Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
||S = 1, R = 0, E = 1
- Output of NAND-3 i.e. R’ = 0 and output of NAND-4 i.e. S’ = 1.
- Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset condition.
||S = 1, R = 1, E = 1
- As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S’ = R’ = 0.
- Hence the Race condition will occur in the basic NAND latch.