S-R Flip-Flop

Posted By on September 30, 2014


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Flip-Flops
Master Slave JK Flip Flop

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E= 1 but there is no change in the output if E = 0.

Block Diagram

Block Diagram of SR Flip Flop

Circuit Diagram

Circuit Diagram of SR Flip Flop

Truth Table

Truth Table of SR Flip Flop

Operation

S.N. Condition Operation
1 S = R = 0 : No change
  • If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
  • Hence R’ and S’ both will be equal to 1. Since S’ and R’ are the input of the basic S-R latch using NAND gates, there will be no change in the state of outputs.
2 S = 0, R = 1, E = 1
  • Since S = 0, output of NAND-3 i.e. R’ = 1 and E = 1 the output of NAND-4 i.e. S’ = 0.
  • Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
3 S = 1, R = 0, E = 1
  • Output of NAND-3 i.e. R’ = 0 and output of NAND-4 i.e. S’ = 1.
  • Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset condition.
4 S = 1, R = 1, E = 1
  • As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S’ = R’ = 0.
  • Hence the Race condition will occur in the basic NAND latch.
Flip-Flops
Master Slave JK Flip Flop

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Posted by Akash Kurup

Founder and C.E.O, World4Engineers Educationist and Entrepreneur by passion. Orator and blogger by hobby

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