Pin Diagram of 8086

Posted By on September 15, 2014


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The Bus Interface Unit
Comparison between Minimum mode and Maximum mode

 

indexFig: Pin Diagram of 8086

Following figure shows the logical pin diagram of 8086 microprocessor. All the signals can be classified into six groups:

1. Power supply and frequency signals.

2. Clock signal

3. Address bus.

4. Data bus.

5.Mode selection.

6. Control and status signals.

7. Externally initiated signals, including interrupts.

 

  1. Power supply and frequency signals

Vcc is on pin 40 supplies +5V power supply.

Pin 1 and 20 for ground reference.

  1. Clock signal

Pin 19 for clock input (CLK): an 8086 requires a clock signal from some external, crystal-controlled clock generator to synchronize internal operations in the processor with maximum frequencies ranging from 5 MHZ to 10 MHZ.

  1. Multiplexed address/data Bus

AD0 through AD15 are used at the start of machine cycle to send out addresses and later in the machine cycle they are used to send or receive data. (This is also known as multiplexing the bus.) However, the-low order address bus can be separated from these signals by using a latch.

  1. Multiplexed address bus

The 8086 has 4 signal lines A16/S3 through A19/S6. The double mnemonic on these pins indicates that address bits A16 through A19 are sent out on these lines during the first part of a machine cycle and the status information, which identifies the type of operation to be done in that cycle, is sent out on these lines S3 through S6 during a later part of the cycle.

  1. Mode selection

The operating mode of the 8086 is determined by the logic level applied to the MNoverline{MX} input on pin 33. If pin 33 is asserted high, then the 8086 will function in minimum mode, and pins 24 through 31 will have the functions shown in parentheses next to the pins i.e. overline{INTA}, ALE, overline{DEN}, DT/overline{R}, M/overline{IO}, overline{WR}, HLDA, and HOLD. If the 8086 is in minimum mode in systems, it works as a single microprocessor on the system buses.

If the MNoverline{MX} pin is asserted low, then the 8086 is in maximum mode. In this mode pins 24 through 31 will have the functions described by the mnemonics next to the pins i.e. QS1, QS0, overline{S0}, overline{S1}, overline{S2}, overline{LOCK}, overline{RQ}/overline{GT1}, and overline{RQ}/overline{GT0}. If the 8086 is in maximum mode in systems, it has two or more microprocessors sharing the same buses and this mode is called multiprocessor mode.

  1. Control and status signal

This group of signals is to identify the nature of the operations. These signals are as follows.

  1. ALE- Address Latch Enable (pin 25): this is a positive going pulse generated every time the 8086 begins an operation (machine cycle).This output signal indicates the availability of the valid address is on the address/data lines.
  2. overline{RD} (pin 32) Read: This is read control signal (active low). This signal indicates that the selected I/O or memory device is to be read and data are available on the data bus.
  3. overline{WR} (pin 29) Write: This is a write control signal (active low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O location.
  4. M/overline{IO} (Pin 28): when it is high, reading from and writing to a memory location, and if it is low, reading from and writing to a port.
  5. overline{S0},overline{S1},overline{S2} (pins 26, 27 and 28): these control bus signals are sent out encoded form of data and an external bus controller device decodes these signals to produce the control bus signals required for a system which has two or more microprocessors sharing the same buses.
  6. overline{DEN}(pin 26) Data Enable signal: it is used to enable bidirectional buffers on the data bus, when DEN is low. i.e. it send data out on the data bus and read the data in on the data bus.
  7. DToverline{R} (pin 27) Data transmit/receive signal: when  DToverline{R} is high, the 8086 is used to decide the direction in which the buffers are enabled through the DENthe 8086 transmit the data to ROM, RAM, or ports. when  DToverline{R} is low, the buffers will allow data to come in from ROM, RAM, and ports.
  8. overline{BHE}/S7 (pin 34) Bus high enable:  The bus high enable is used to indicate the transfer of data over the higher order data bus  If it goes low, the address that it will be writing to on AD0 –  A19.
  9. Interrupts and Externally initiated signals:
  10. NMI (Nonmaskable interrupt pin 17) and INTR (interrupt pin 18) input :A signal can be applied to one of these inputs to cause the 8086 to interrupt the program  it is executing and go execute a specified procedure.
  11. HOLD input (pin 31): when the HOLD line is high , this signal indicates that a peripheral such as a DMA (DMA Direct memory Access) controller is requesting the use of the address and data buses.
  12. HLDA (pin 30) Hold Acknowledge:  This signal acknowledges the HOLD request.
  13. READY input (pin 22): This signal is used to delay the microprocessor Read or Write cycles until a slow responding peripheral is ready to send or accept data. When this signal goes low, the microprocessor waits for an integral number of clock cycles until it goes high.
  14. RESET (pin 21): This signal indicates that the MPU (microprocessor) is being reset. The signal can be used to reset other devices.
The Bus Interface Unit
Comparison between Minimum mode and Maximum mode

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Posted by Akash Kurup

Founder and C.E.O, World4Engineers Educationist and Entrepreneur by passion. Orator and blogger by hobby

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