Emitter-coupled logic (ECL)

Posted By on December 15, 2014


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TTL NAND and AND gates

Emitter-coupled logic (ECL) is one of the many bipolar logic families commercially available. ECL achieves the fastest possible switching times in circuits today by operating in active mode instead of saturation. This non-saturating logic is a different family than the RTL, DTL, and TTL families, which use saturated bipolar transistors to achieve logic functions. ECL is limited because of its high power dissipation and large silicon requirements, thus it is mostly used in small and medium scale integrated circuits. Due to this large power dissipation, it has a very limited range of operating voltages.

DescriptionFig. 1: ECL Gate

As you can see in the basic circuit diagram, this circuit has the emitter-coupled differential amplifier (Q 1, Q 2, R 1 & R 2) present in all ECL circuits. When VIN is at logic low, Q2 is in forward active mode, and Q 1 is off. As V IN approaches V IL, Q 1 turns on, and both transistors are in forward active mode until we pass V IH, where Q 2 turns off. All other transistors operate in forward active mode regardless of the input voltage. As V IN approaches 90% of V CC, Q 1 saturates, causing the slight rise in VO1, as seen in the VTC.

This circuit has two uses. V O1 can be used as an inverter, while V O2 can be used as a non-inverting buffer. Due to the high power dissipation of this circuit (as seen in figure 6), a CMOS inverter/non-inverting buffer would be more efficient and more appropriate, unless extremely high switching speeds are necessary.

TTL NAND and AND gates

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Posted by Akash Kurup

Founder and C.E.O, World4Engineers Educationist and Entrepreneur by passion. Orator and blogger by hobby

Website: http://world4engineers.com