Delay Flip Flop / D Flip Flop

Posted By on September 30, 2014


Download PDF
Master Slave JK Flip Flop
Toggle Flip Flop / T Flip Flop

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1,these input condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Block Diagram of D Flip Flop

Circuit Diagram

Circuit Diagram of D Flip Flop

Truth Table

Truth Table of D Flip Flop

Operation

S.N. Condition Operation
1 E = 0
  • Latch is disabled. Hence is no change in output.
2 E = 1 and D = 0
  • If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the reset condition.
3 E = 1 and D = 1
  • if E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.
Master Slave JK Flip Flop
Toggle Flip Flop / T Flip Flop

Download PDF

Posted by Akash Kurup

Founder and C.E.O, World4Engineers Educationist and Entrepreneur by passion. Orator and blogger by hobby

Website: http://world4engineers.com