Core-2-Duo: Key Features and Technical Specifications
Key Features of Core-2-Duo:-
- 64 bit support
- Dual core processor with shared level 2 cache
- Execute Disable Bit
- Partially Intel Virtualization Technology (VT)
- Socket M (starting from Santa Rosa socket P)
- 291 million transistors
The Core 2 Duo processors are produced in 65 nm (and later in 45nm), contain 14 stages pipelines and 2-4 MB level 2 cache (depending on the model). The features of the Core 2 Duo are:
The Intel Core 2 Duo uses the x86 instruction set, which was introduced in 1978 with the 8086/8088 processor. Furthermore it supports the multimedia extension MMX, SSE2, SSE3 and SSE4.
Dual core technology
Two processor cores run with the same frequency in the same processor building block and share the level 2 cache as well as the front side bus (FSB).
Execute Disable Bit
Prevents security problems through buffer overflows, if the operation system supports it and if it is activated.
Wide Dynamic Execution *
Every core can execute four complete commands simultaneously.
Shorter idle times, improved data transfer and faster out-of-order command execution lead to better usage of the pipeline and as a result to higher performance.
Like the Core Duo, the Core 2 Duo has shared level 2 cache and each core receives the same amount of cache. Intel doubled the bandwidth to the level 1 cache though.
One 128-Bit SSE command is now output per clock cycle.
Virtualisation technology (VT)
The Intel VT offers hardware support for virtual systems on one computer (use of several isolated operation systems at the same time e.g. through Xen or VMWare).
Beware, not all models support VT (especially the cheaper ones dont).
64 bit support *
Support of 64 bit wide words in the CPU. This means the processor can handle 64 bit data packets. The Intel Core 2 Duo supports the AMD64 extension (licensed), through which 32 and 64 bit programs can run on the CPU (if a 64 bit operation system is used).
Theoretically, a 64 bit processor can access more than 4 GB of memory, but this is usually limited by the chip set used.
* This feature was newly introduced with the Core 2 Duo.
Energy saving functions
Like with the previous version, the clock rate and voltage can be set dynamically and individually for each core (Speedstep). Under light load the processor can save energy by lowering the clock speed (to 1200 MHz respectively 800 MHz with the Santa Rosa) and the core voltage (from 1.3 Volt to 1.0375 Volt). This happens with virtually no performance losses, thanks to the automatic adjustment of the clock speed. Additionally, the processor can turn off parts of the CPU which are not used, to save energy.
Intel Dynamic Power Coordination
Coordinates the Enhanced Intel SpeedStep technology and the Idle Power-Management State (C-state) transitions independent of the core.
Enhanced Intel Deeper Sleep with Dynamic Cache Sizing
Writes data from the cache to the main memory during inactivity. As a result, the CPU voltage can be lowered which saves energy.
Intel Dynamic Bus Parking
Allows the chip set to shut down during inactivity to save energy.
Advanced Power Gating
Parts of the CPU core can be shut down through “Advanced Power Gating”. This can even happen if performance is required, to improve the performance per watt ratio.
Enhanced Deep C4 Sleep State
The core voltage can be further reduced, if the level 2 cache is turned off.
Split Bus Array
Buses and arrays are separated in order to set them individually into energy saving mode during certain operation states.