# Asynchronous or Ripple Counter

Posted By on September 30, 2014

## Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle(T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-B.

### Operation

S.N. Condition Operation
1 Initially let both the FFs be in the reset state QBQA = 00…………….initially
2 After 1st negative clock edge
• As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1.
• QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF.

QBQA = 01…………….After the first clock pulse

3 After 2nd negative clock edge
• On the arrival of second negative clock edge, FF-A toggles again and QA = 0.
• The change in QA acts as a negative clock edge for FF-B. So it will also toggle, and QB will be 1.

QBQA = 10…………….After the second clock pulse

4 After 3rd negative clock edge
• On the arrival of 3rd negative clock edge, FF-A toggles again and QA become 1 from 0.
• Since this is a positive going change,FF-B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1.

QBQA = 11…………….After the third clock pulse

5 After 4th negative clock edge
• On the arrival of 4th negative clock edge, FF-A toggles again and QA become 1 from 0.
• This negative change in QA acts as clock pulse for FF-B. Hence it toggles to change QB from 1 to 0.

QBQA = 00…………….After the fourth clock pulse

## Truth Table

#### Posted by Akash Kurup

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